1. Technical Field
The present invention relates generally to an improved data processing system and in particular to a transfer of data within a data processing system. Still more particularly, the present invention relates to a method and apparatus for transferring signal pulses between clock domains within a data processing system.
2. Description of the Related Art
Computer technology is continuously advancing, resulting in modern computer systems which provide ever increasing performance. As computer systems become more advanced, more and more components are being added to computer systems and the number of transistors within these components is ever increasing.
One artifact of increasing computer system components and transistors is the generation of multiple clock signals. Different components within the computer system are typically driven by (also referred to as "referenced to") clock signals having different frequencies. Components which are driven by a particular clock signal are referred to as operating in the clock domain of that particular clock signal.
In addition, different functional blocks within the components may also be driven by clock signals having different frequencies. For example, a computer system may include a processor coupled to a bus and an interrupt controller, where the interrupt controller generates signals on a serial bus which is referenced to a first clock signal, the bus is referenced to a second clock signal, and the processor core is referenced to yet a third clock signal. Synchronizers are typically used in computer systems to allow different components operating in different clock domains to communicate with one another. When a component operating in a first clock domain sends a signal to a component in a second clock domain, the signal is sent through a synchronizer so that the timing of the signal is synchronized to the second clock domain.
Presently available synchronizers typically use an edge detection technique that relies on an asynchronous feedback path to clear the edge detection. An example of such a circuit is found in FIG. 1 in which synchronizer circuit 100 includes an input unit 102 and a synchronizer unit 104 in which an input signal from the first clock domain is received at input 106 and input unit 102. This input signal is sent to synchronizer unit 104 which sends data out into the second clock domain at output 108. The synchronization to the data to the second clock domain is controlled by a destination clock signal applied to input 110. The asynchronous feedback path is formed by the connection from output 108 and synchronizer unit 104 to the connection at input 112 and input 102. This circuit has a disadvantage of not being compatible with newer synchronous design requirements that require support of scan testing and static timing. Therefore, it would be advantageous to have an improved method and apparatus for synchronizing signals for transmission between clock domains.